1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to phase rotation of signals within such communication systems.
2. Description of Related Art
Data communication systems have been under continual development for many years. Sometimes within such communication systems, there is a need to perform rotation of signals (e.g., by changing the phase of such signals). For example, within a wide variety of applications (e.g., serializers, de-serializers, and/or other communication devices, etc.), there may be a need to generate a signal having a desired phase.
Traditional, prior art embodiments of N step phase rotators employ control signals including N bits. As N or the number of required phase rotators increases, the necessary control signal routing and congestion also increases. As this number increases, the digital to analog (D/A) interfacing becomes a challenging design issue.
FIG. 2 illustrates an embodiment of a prior art apparatus 200 implemented to perform phase rotation. In this embodiment, clock signals are provided to 4 different differential pairs of transistors, as shown by differential pair 0°, differential pair 90°, differential pair 180°, and differential pair 270°.
A very large control word (e.g., 256 bits in this embodiment) is employed to control the connectivity of 256 corresponding switches. In this embodiment, 64 separate current sources and/or supplies (shown as Io-1 to Io-64), and each current supply is coupled to ends of 4 of the switches.
The switches are arranged in groups of 4, such that current from any one current supply is only directed through one of the switches in each group of 4 to only one of the differential pairs of transistors. As can be seen, this prior art approach includes a significant number of control signals (e.g., 256 in this embodiment), and this can consequently lead to significant congestion and consumptive of real estate within this prior art approach.
Because of the very large number of control signals within the prior art apparatus 200 and this prior art approach, congestion and routing clearly become significantly complex design issues. Alternatively, considering the 256 control signal prior art embodiment as an illustration, to avoid this issue of such a very large number of control signals, sometimes a decoder is employed that receives 7 separate signals and then decodes those 7 signals to generate the 256 control signals. However, this decoder implementation can sometimes create glitches within the 256 control signals. To address the glitch problems, a number of flip-flops (FFs) can be added, but the FFs do add some latency to the overall architecture. If latency is not a concern, then the FF approach adequately deals with the glitch problems. However, generally speaking, increasing and/or changing the latency of an overall data recovery loop is undesirable. Also generally speaking, smaller data recovery loop latency is desirable.
FIG. 3 illustrates an alternative embodiment of a prior art apparatus 300 implemented to perform phase rotation. This embodiment 300 is analogous to the previous embodiment, and this embodiment shows the connectivity of the differential pairs of transistors and how the various clock signals are provided to their respective gates. For example, a first clock signal having a phase of 0° is provided to differential pair 0°, a second clock signal having a phase of 90° is provided to differential pair 90°, a third clock signal having a phase of 180° is provided to differential pair 180°, and a fourth clock signal having a phase of 270° is provided to differential pair 270°.
The sources of each differential pair are coupled together and that node is also coupled to one switch within each of the groups of 4 switches. For example, the sources of the differential pair 0° are coupled together and that node is coupled to the switches controlled by ctrl1, ctrl5, and so on up to ctrl253, respectively. The sources of the differential pair 90° are coupled together and that node is coupled to the switches controlled by ctrl2, ctrl6, and so on up to ctrl254, respectively.
The sources of the differential pair 180° are coupled together and that node is coupled to the switches controlled by ctrl3, ctrl7, and so on up to ctrl255, respectively. The sources of the differential pair 270° are coupled together and that node is coupled to the switches controlled by ctrl4, ctrl8, and so on up to ctrl256, respectively.
When crtl1 closes its corresponding switch, then the other of the control signals that control that group of 4 switches will keep those other 3 switches open (e.g., crtl2, crtl3, and crtl4 keep their corresponding switches open), and current from current source Io-1 is directed to the sources of the differential pair 0°.
When crtl2 closes its corresponding switch, then the other of the control signals that control that group of 4 switches will keep those other 3 switches open (e.g., crtl1, crtl3, and crtl4 keep their corresponding switches open), and current from current source Io-1 is directed to the sources of the differential pair 90°.
If all current from all of the current sources Io-1 to Io-64 is directed to the differential pair 0°, then the output signal (shown as outn/outp) has a phase of 0°. If all current from all of the current sources Io-1 to Io-64 is directed to the differential pair 90°, then the output signal (shown as outn/outp) has a phase of 90°.
If all current from all of the current sources Io-1 to Io-64 is directed to the differential pair 180°, then the output signal (shown as outn/outp) has a phase of 180°. If all current from all of the current sources Io-1 to Io-64 is directed to the differential pair 270°, then the output signal (shown as outn/outp) has a phase of 270°.
If the current from one half of the current sources (e.g., Io-1 to Io-32) is directed to the differential pair 0°, and the current from one half of the current sources (e.g., Io-33 to Io-64) is directed to the differential pair 90°, then the output signal (shown as outn/outp) has a phase of 45°.
Also, if three fourths of the current sources (e.g., Io-1 to Io-16) is directed to the differential pair 0°, and the current from one fourth of the current sources (e.g., Io-17 to Io-64) is directed to the differential pair 90°, then the output signal (shown as outn/outp) has a phase of 22.5°.
By directing the current from the current sources (e.g., Io-1 to Io-64) to two different differential pairs of transistors in a particular manner, then a signal having any desired phase (as controlled by the limits of the step size of the device) in between the phases of the clock signals provided to those two different differential pairs of transistors can be generated and output via the selectively coupled drains of the differential pairs of transistors (as shown by outn/outp).
As can also be seen in this embodiment, load impedances (e.g., resistors) may be coupled between the selectively coupled drains of the differential pairs of transistors to a power supply voltage (e.g., VDD or VSS).
FIG. 4 illustrates an alternative embodiment of a prior art apparatus 400 implemented to perform phase rotation. This embodiment is analogous to the previous embodiments, but this embodiment employs 8 differential pairs of transistors. For example, 8 different clock signals are provided to the 8 differential pairs of transistors. A clock signal having a phase of 0° is provided to differential pair 0°, a clock signal having a phase of 45° is provided to differential pair 45°, a clock signal having a phase of 90° is provided to differential pair 90°, a clock signal having a phase of 135° is provided to differential pair 135°, a clock signal having a phase of 180° is provided to differential pair 180°, a clock signal having a phase of 225° is provided to differential pair 225°, a clock signal having a phase of 270° is provided to differential pair 270°, and a clock signal having a phase of 315° is provided to differential pair 315°.
This embodiment also includes a very large control word (e.g., 256 bits in this embodiment) is employed to control the connectivity of 256 corresponding switches. In this embodiment, 32 separate current sources and/or supplies (shown as Io-1 to Io-32), and each current supply is coupled to ends of 8 of the switches. The switches are arranged in groups of 8, such that current from any one current supply is only directed through one of the switches in each group of 8 to only one of the differential pairs of transistors. As can be seen, this prior art approach includes a significant number of control signals (e.g., 256 in this embodiment), and this can consequently lead to significant congestion and consumptive of real estate within this prior art approach.
As can be seen within these prior art approaches, there is a great deal of control signaling and routing therein. There exists a need in the art a better means by which phase rotators may be implemented.